Guarantee & Conformity

The SPEED7 Processor guarantees high design reliability due to more than 20.000 test procedures during the complete development period. In October 2002, the first available prototypes were tested in more than 130 real STEP^®7 (from Siemens) customer applications (status August 2003). Intensive RTL and Gate-Level-Simulations were completed in order to eliminate possible faults and to ensure the functionality of the chips.

The improvements for In-System-Tests by using FPGA Prototypes have helped the SPEED7 Processor attain the highest reliability levels. A "Late Error Correction Unit ( LEC)" is integrated to account for unexpected incompatibilities. The LEC can deactivate unknown OP Codes and forward the data to the Host-Processor.

Illustration:
Memory block for timer on the SPEED7 Chip. The memory is locked from several supply voltage rings. In the block on the left hand side, there is the memory cell, the control logic is in the middle on the right hand side. The amplifier is on the right hand side. The timer unit has with a resolution of 0.001ms.